The hottest pin to PWM signal source regulates the

2022-10-01
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Regulating motor driver IC for PWM signal source

how to connect PWM logic signal source to battery powered motor driver is a difficult problem we face. This paper introduces the design method of connecting motor driver to PWM source, including related equations and component selection guide. The circuit used in this method includes examples with accuracy and sensitivity analysis

connect the motor driver to the small tonnage M source of PW ordinary plastic experimental machine

lm4570 is an eccentric rotating mass (ERM) and linear resonance excitation (LRA) motor drive IC, which is suitable for mobile and other portable media devices. The design of this paper describes in detail the setting process of connecting lm4570 to PWM source

although the LRA motor is driven by AC bipolar waveform at a resonant frequency close to LRA, ERM motor is mainly driven by DC voltage. Due to the need to use DC, there may not be AC coupling capacitors connected in series with the input of the driver IC

designing the PWM interface connected to the driver IC requires a lot of mathematical knowledge to ensure correct operation

the first step in designing this circuit is to determine the required gain. PWM source can provide the following voltage levels:

where VIN (peak) is the single terminal peak output voltage that PWM source can provide, and VLOGIC is the PWM logic high voltage under the action of large enough alternating stress. If the PWM source can achieve a duty cycle of 0% and 100%, please use equation 1. If the PWM source cannot reach the duty cycle of 0% and 100%, please use equation 1a, because VIN (peak) needs to be reduced accordingly according to this equation:

where DC (max) and DC (min) are the maximum and minimum duty cycles of the PWM source respectively. Please select 1. All frames are constructed with DC (max) or DC (min) so that the minimum VIN (peak) item can be generated to ensure symmetrical swing

the next step is to determine the peak output voltage Vout (peak) required to flow through the ERM motor. In order to achieve consistent operation at all battery voltages, this value can be set to 3V or lower, or 4.2V to obtain maximum overspeed drive with sufficient battery power. The peak output voltage must be checked according to the ERM motor specification to ensure that its amplitude and duration do not exceed the specification specified by the ERM motor manufacturer. We can use Vout (peak) and VIN (peak) to calculate the system gain:

where "gain" is the gain required from the single ended PWM source to the output of the bridged load (BTL) amplifier

the analysis of the required gain of the circuit in Figure 1 shows that the 2x gain of the BTL output needs to be corrected, and the resistance can be calculated by the following formula:

the simplest method is to select RF as 200K, and then calculate the sum of Rg1 and Rg2. RG is divided into two resistors to allow the addition of a bypass capacitor CF to form a first-order low-pass filter. This low-pass filter can prevent the high-frequency content from the PWM signal from being radiated by the amplifier and ERM motor. Choose Rg1 and Rg2 as basically the same value, then use their sum and calculate the required gain through equation 3. The cut-off frequency of the low-pass filter can be calculated by the following formula:

where f-3db is the cut-off frequency of the low-pass filter, which is usually set to 2KHz to 5KHz

the last step in designing this circuit is to correctly increase the bias voltage for ref2 (see Figure 1). The reason why this must be done is that the average DC level of the PWM source (half VLOGIC) is different from the average DC level of the output (half vbattery change value). Select resistors R1 and R2 in Figure 1 to complete this operation. Please note that REF1 can be widely used in the pendulum impact experiment of industrial and mining enterprises, scientific research institutions and quality inspection departments on plastic, rubber and other materials. The Thevenin impedance of the pin is about 10K, so we will choose R2 to be about 200K, so that the loading effect can be ignored. The calculation formula of bias voltage is as follows:

Figure 1: lm4570 motor driver with PWM interface

where R1 is the impedance equivalent to R1a and r1b in parallel (forming the partial voltage of these two resistors). Similarly, assuming that the duty cycle of PWM input is 50% and the output is balanced with vdd/2, the voltage calculation formula of in end can be obtained:

it is obvious that formula 5 and formula 6 are actually the same in form, so we can find that we only need to make R2 equal to RF and make R1a and r1b twice the RG value. One advantage of using a symmetrical circuit is that the VDD term is removed from the calculation formula, so that the circuit is no longer sensitive to changes in battery voltage

in order to test these formulas, we will use an example with the following parameters: vlogic=1.5v, Vout (peak) =3.0v

to obtain the above value, we need the "gain" to reach 4. Choose RF as 200K and use equation 3 to calculate that RG is equal to 100k, or Rg1 and Rg2 are equal to 49.9k. Since these two parts are symmetrical, choose R2 as 200K and use equation 3 again to calculate that R1 is equal to 100k, or R1a and r1b are equal to 200K. In order to evaluate the performance of the circuit, we scan the input duty cycle from 0% to 100%, and gradually increase the battery voltage from 3.0V to 3.6V to 4.2V. In addition, we use Monte Carlo analysis to detect the resistance value to judge its sensitivity (the results are shown in Figure 2)

Figure 2: simulation results

as shown in Figure 2, Vo1 and VO2 are complementary to each other. Please note that the two signals always intersect at zero at the 50% duty cycle point or 0.75V on the input. Even when the battery voltage changes within its available range, it will intersect at half of the battery voltage

the simulation in Figure 2 is also a Monte Carlo scan with a resistor tolerance of 1%. As shown in the figure, each route is slightly widened, which means that there is only a negligible impact on performance

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